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SEMICONDUCTOR TECHNICAL DATA
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MC141622EVK ACF-II Evaluation Board Operating Manual
1. SUMMARY The MC141622EVK is a development board for evaluation of the MC141622. In addition to the MC141622, the MC141622EVK contains all the analog circuit that is necessary for buffering both the input and output video signal and generation of the 4xfsc clock. By connecting an external signal source, monitor, and power supply, it is possible to evaluate all the operating modes on the MC141622. 2. SPECIFICATION Board Dimensions Y/C Separation LSI Video Input Amplifier Video Output Amplifier Clamp Circuit Clock Generator Clock Buffer Amplifier Analog Input/Output Interface Digital Input/Output Interface Action Mode Regulator Recommended Supply Voltage Operating Temperature Supply Current 100 mm (Length) x 150 mm (Width) MC141622FU Mount MC14577 2SC2002 Use MC14576 Use 2SC2002 2SA953 Use MC1378P Use MC14576 Use BNC Connector x3, S Terminal Output Mount 16 Pin Header Mount MC141622 Supports All Operating Modes MC7805CT Use + 10 V 0 to 50C 350 mA
REV 3 1/97 TN97012000
(c) Motorola, Inc. 1997 MOTOROLA
MC141622EVK 1
3. BOARD OPERATION 3.1 ACF-II Operating Mode AFC-II has four operating modes. Any one of these modes can be selected using the digital code input to MODE 0 and MODE 1 using ROTARY SW. The function of each mode is as follows. (1) Normal fsc Mode This is the mode for usual Y/C separation. It separates Y/C from the video signal that is input to the A/D converter. The coring parameter of the vertical enhancer can be set up by the digital code that is input to C0 - C3 (block level parameter), C4 - C7 (white level parameter), and D4 - D7 (noise slice level parameter). The clock is a 3.579545 MHz subcarrier input to the CLK connector; the built-in 4x PLL generates 4xfsc clock. (2) Normal 4xfsc Mode This mode is used for Y/C separation. It separates Y/C from the video signal that is input to the A/D converter. The coring parameter of the vertical enhancer can be set up by the digital code that is input to C0 - C3 (block level parameter), C4 - C7 (white level parameter), and D4 - D7 (noise slice level parameter). The clock is 14.31818 MHz which is a 4x subcarrier input to the CLK connector. (3) Digital Input Comb Filter Mode This mode uses the A/D converter, filter, and D/A converter as two independent blocks. The digital data converted by the A/D converter is output on C0 - C7. Data input on D0 - D7 is processed by the ACF-II. Filtering is performed by the algorithm of ACF-II and the Y/C video is output as analog signals from Yout and Cout. These two blocks can operate with input clock signals that have different frequencies or phases and can be operated independently by using the CLK(AD) for the A/D converter, and the CLK input for the D/A converter. The clock is 14.31818 MHz which is a 4x subcarrier input to the CLK connector and the CLK(AD) connector. (4) Digital Output Comb Filter Mode In addition to the normal Y/C analog outputs, the MC141622EVK can provide the Y/C signals as digital luminance and chrominance signals. The digital luminance data is output on C0 - C7 and the digital chrominance data is output on D0 - D7. This digital data can be modified by other digital processing.
MC141622EVK 2
MOTOROLA
The following table is the assignment for the operating mode. MODE Switching Function
Mode Normal fsc Mode Normal 4xfsc Mode Digital Input Comb Filtering Mode Digital Output Comb Filtering Mode MODE1 L L H H MODE0 L H L H Rotary SW 0 1 2 3
4. BK FUNCTION By setting the BK pin (toggle SW1) to the H level, composite video is output on the Yout pin and the chrominance signal on the Cout pin. The following table is the function of the BK pin. BK Function
BK Pin L H Yout Pin Luminance Composite Cout Pin Chrominance Chrominance
4.1 Vertical Enhancer Function By setting the VH pin (toggle SW2) to the L level, the vertical enhancer feature is enabled. The coring parameter of the vertical enhancer can be set up every 1 LSB by the digital code that are input to C0 - C3 (black level parameter), C4 - C7 (white level parameter), and D4 - D7 (noise slice level parameter. The set up level of the coring parameter and characteristics are as follows. Coring Characteristics
OUT OUT WHITE LEVEL (C4 - C7) (0 - 15 STEP) IN BLACK IN C7 C3 D7 L L L L IN BLACK LEVEL (C0 - C3) (0 - 16 STEP) L L L L H H H H H H H H
Vertical Enhancer Function
VH Pin L H Vertical Enhancer On Off
WHITE
Coring Parameter Set Up
C6 C2 D6 L L L L H H H H L L L L H H H H C5 C1 D5 L L H H L L H H L L H H L L H H C4 C0 D4 L H L H L H L H L H L H L H L H 0 1 2 3 4 5 6 7 8 9 A B C D E F Level L l
OUT
OUT
IN NOISE LEVEL (D4 - D7) (0 - 15 STEP)
MOTOROLA
MC141622EVK 3
4.2 Clock Generator Compounding The clock generator (MC1378P) provides the necessary reference oscillator and phase locks the clock to the color subcarrier by inputting the composite video signal. VC1 adjusts the horizontal VCO to synchronize the output of the burst gate (pin 5 on the MC1378P) with the input video signal. VC2 adjusts the chroma VCO for maximum amplitude output from the clock buffer (pin 1 on the MC14576). VR3 adjusts pull-in of the chroma PLL filter. This is usually fixed to the center position. VR4 selects the dc bias for the clock buffer output and is usually 2.25 V. 4.3 Video Amplifier Adjustment On the video amplifier (MC14577), the gain is adjusted by VR1. This sets the input range (3.0 Vp-p) of the A/D converter in MC141622FU. VR2 is the clamp level adjustment. This adjusts the sync tip clamping of the input video signal to the video amplifier. 4.4 Outside Interface The outside interface should provide a composite video input signal to BNC1. The MC141622EVK provides Y/C separation and outputs the luminance from BNC2 and the color signal from BNC3. There is an S output connector on this board for easy connection to instruments having an S input connector. BNC4 and BNC5 are for the external input of each CLK and CLK(AD). However, when using these, it is necessary to modify the board pattern; i.e., cut (J5, J6). There is no filter for bandwidth limitations on this board beyond that imposed by the bandwidth limitations of the MC14577 buffer amplifier. To minimize noise resulting from excessive bandwidth, the bandwidth of input video signal should be limited to no more than one half of the clock frequency.
MC141622EVK 4
MOTOROLA
5. MC141622EVK CIRCUIT
47 F + 0.1 F 0.0047 F
470 k
1.0 F 1.0 F 28 27 26 25 24 + 0.1 F 22 + 1.0 F 21 160
0.1 F 40 39 38 37 36 35 34 33 32
0.1 F 31 30
0.1 F 29
23
ADC GND DAC GND DIGITAL GND 1 + TANTALUM CAPACITOR 0.02 F MULTI-LAYER CERAMIC CAPACITOR 680 2 3 4 5 6 7 0.1 F 8 9
MC1378P
10
11 17.7 MHz 14.3 MHz
12 0.1 F
13 0.1 F
14 0.1 F
15 0.1 F
16 0.1 F
17
18 1.0 F
19 +
20 0.1 F
4 MHz CER. RES.
4.7 F 2.2 k 7.5 m 4 1 m 5 3 2 1
47 F +
0.1 F 33 H
1 F
+
30 pF
1 k 750 k + 1.0 F
0.001 F
1.8 k
0.1 F 30 pF
MC14576 6 7 8 33 H 47 F + 0.1 F 1 m 0.1 F
10 k x 8
10 k x 8
47 k x 8
47 k x 8
VCC(D) 5V
5
33 H 47 k x 4 ROTARY SW VIDEO IN BNC1
+ 47 F
0.1 F J6
D4
D5
D6
D7
C0
C1
C2
C3
C4
C5
C6
C7
VCC(A) 10 V
1.0 F
36 35 34 + 47 F 0.1 F 10 k x 2 J5 D3 D2 D1 D0 BK VH VCC(D) 5V CLK BNC4 33 H SW GND (D) VCC(D) FSC NC NC NC 37 38 39 48 41 42 43 44 45 46 47 48 1 PCO 2 OVCC 3 BIAS
33 32 31
30
29 28 27 26 25 24 23 22 21 20
TE1 TE0 MODE1 MODE0 CLK(AD) GND(D) VCC(D) CLC CLout Vin RBT RTP 1.0 F 0.33 F CLK(AD) BNCS 750 k
33 H
33 H
160
47 F
+
0.1 F
47 F
+ 0.1 F C2002
2.2 k
2.2 k
MC141622
19 18 17 16 15 14 13
C2002 1 4
8 + -
3 2 2.2 k CLAMP LEVEL
MC14677
2 k
2 k
1 k GAIN ADJUST
610
610 k
A953
4 FL IN
5 GND(DA)
6 Yout
7
8
9 REF(DA)
10 11 I bias GND(AD)
12 VCC(AD)
VCC(DA) Cout
VCC(A) 10 V
33 H 47 F
200
47 F
+ 0.1 F 9.1 k
43 k
33 H
0.1 F
10 k
VCC(D) 5V
10 F
+ 0.1 F
+ 10 F
0.1 F
+
0.1 F 8 3 2
33 H + 47 F 0.1 F + 47 F VCC(A) (5 V) 47 F + 0.1 F 33 H VCC(A) (10 V)
7 k Yout BNC2
1 4
+ -
Vout MC7805CT
Vin + 0.1 F
1/2MC14678 8 7 4 5 6
4.7 + 0.1 F F
4.7 F GND
7 k Cout BNC3
+ -
2/2MC14678
MOTOROLA
MC141622EVK 5
6. MC141622EVK PARTS LIST
Reference Designation IC1 IC2 IC3 IC4 IC5 IC6 TR1 TR2 TR3 R1 R2 R3, R4 R5 R6 R7, R8 R9 R10 R11 R12, R13 R14 R15 R16 R17 R18 R19, R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 L1 - L9 L10 L11 VR1 VR2 VR3 VR4 VC1, VC2 SW1, SW2 DIP SW1, DIP SW2 ROTARY SW Description MC141622FU MC14576CP MC14577CP MC7805CT MC14576CP MC1378P 2SC2002 2SC2002 2SA953 9.1 k 62 k 75 3.6 k 750 k 2.0 k 510 150 510 k 2.2 k 47 k x 4 47 k x 8 10 k x 8 47 k x 8 10 k x 8 10 k x 4 200 1.8 k 680 750 k 2.2 k 7.5 m 1.0 m 150 470 k 33 H 4.7 H 33 H 1 k 2.2 k 1 k 1 m 30 pF Toggle Switch 8 Channel Dip Switch 16 Channel Switch 4 MHz Cer. Res 14.32 MHz Crystal Reference Designation C1 C2, C3 C4, C5, C6 C7 C8 C9 C10 C11 C12 C13 C14, C15 C16 C17 C18 C19 C20, C21 C22 C23 C24 C25 C26 C27 C28 C29, C30 C31 C32 C33, C34 C35 C36 C37 C38 - C45 C46 C47, C48 C49 - C51 C52 C53 C54 C55 - C57 Description 0.1 F 47 F 0.1 F 47 F 0.1 F 10 F 0.1 F 10 F 0.33 F 1.0 F 0.1 F 47 F 0.1 F 1.0 F 47 F 0.1 F 47 F 0.1 F 47 F 0.1 F 47 F 10 F 0.1 F 47 F 0.1 F 0.022 F 1.0 F 0.1 F 0.001 F 47 F 0.1 F 1.0 F 0.1 F 1.0 F 0.1 F 47 F 0.047 F 0.1 F
MC141622EVK 6
MOTOROLA
7. MC141622EVK LAYOUT
L11 C57 C56 C55 C54 C53 C51 C50 C52 C49 C48 R28 C29 MC1378P C30 C31 L8 R22 C32 C33 VC1 IC8 C21 C41 C42 C43 C44 C45 C46 C47 C22
7805CT IC4 C24 C23
C31
4 MHz R28
POWER
C34 R24 L10 C40 L9 VR4 C37 VR3 C38 VC2 C17 SETTING VIDEO AMPLITUDE
L4
BNC1 C20 R16-1 C19 R8 R9 C18 R12 R11
L5 R13
R25 C36
14.32
VIDEO IN
R26 R27 MC14576 IC6
MC14577 IC3
SETTING CLAMP LEVEL
C39 J6
R7
VR1 TR1
TR2
BNC5
ROTARY SW C15
R6 C13 J3
C12
CLK(AD) R4 C-PORT C14
C10 C11 C8 C9 C7 L3 C6 J2
TR3
C16
VR2
BNC2
PIN HEADER
DIP SW2
Yout R5 S CONNECTOR CLK BNC3 Cout R4 R3
R16
R15
MC141622 C1 IC1
L1
J1
C2
IC2 R2 PIN HEADER DIP SW1 R18 C3 C25 R19 D-PORT SW1 SW2 C26 R20 R1 C27 R21 C28 C29
R17
L6
R7
OFF
ON
J5
BK
ON
VERTICAL ENHANCE
OFF
J4 BNC4 CLK
C4
MC14576
L4
MOTOROLA
MC141622EVK 7
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 303-675-2140 or 1-800-441-2447 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://www.mot.com/SPS/ JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MC141622EVK 8
MC141622EVK/D
MOTOROLA

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